This invention relates to word driving circuitry for dynamic RAMs. Specifically, a boost clock circuit is provided which will generate clock pulses for driving redundant wordlines and sample word lines of a dynamic memory for either of two clock phases.
High density dynamic memories are routinely implemented with redundant word lines. The redundant wordlines are used when a tested memory has a failure of one or more word lines. When the memory has a defective wordline, it is possible by activating programmable fuses to activate one or more redundant wordlines. In a common dynamic memory organization, rows of memory cells are arranged in blocks of four. Addressing of rows occurs on alternate clock phases.
When a defective row line is replaced by a redundant row line, it is necessary to clock the row driver on either clock phase. Additionally, the dynamic memory is provided with a sample wordline for each section of memory rows which must be activated on either phase of the phase clocks. The reference line will provide a logic reference which is used to distinguish logic states of data produced by an actual row of the memory having data.
The coupling of either clock phase signal to the redundant wordline driver or sample wordline driver must be done with a circuit having a speed which will not significantly increase the access time for the dynamic memory. Further, to adequately reset the row driver clock lines and sample wordline driver clock lines, the coupling must provide a voltage boost below ground to a negative voltage which is more negatiave than the threshold voltage of the array device. Thus, the need for a boost clock which can provide clocking signals for the redundant wordlines and sample wordlines on each phase of the two phases of the phase clock at a speed which does not substantially increase access time is evident.